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5 Stage MIPS Processor
Software Demo and How to use:
A fully functional 5 stage MIPs processor built in a UCSD CSE Lab class. The processor was required to be 5 stages but we went the extra mile to make it also have data forwarding and a hazard detection unit to get the best possible performance. Watch the above video to see it run a fibonacci program.
No repository or code link will be available as this was built for a class assignment and must stay private
Developed in Verilog using Quartus and ModelSim
More than 40+ hours spent on the project.
Collaborative 2 person project.
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